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[Other resource] SystemC片上系统设计源代码

Description: SystemC片上系统设计的源代码： 书籍介绍： SystemC是被实践证明的优秀的系统设计描述语言，它能够完成从系统到门级、从软件到硬件、从设计到验证的全部描述。SystemC 2.01已作为一个稳定的版本提交到IEEE，申请国际标准。 本书为配合清华大学电子工程系SystemC相关课程的教学而编写。全书分9章，内容包括：硬件描述语言的发展史；SystemC出现的历史背景和片上系统设计方法学概述；SystemC的基本语法；SystemC的寄存器传输级设计和SystemC的可综合语言子集，以及根据作者设计经历归结的RTL设计准则和经验；接口、端口和通道等SystemC行为建模实例——片上总线系统；SystemC与VHDL/Verilog HDL的比较；SystemC的验证标准和验证方法学；SystemC开发工具SystemC_win、WaveViewer等，以及使用MATLAB进行SystemC算法模块的验证。每一章都精心编写了课后习题以配合教学的需要。 本书可作为大学电子设计自动化（EDA）相关课程教材，也可供电子工程技术人员作为SystemC设计、应用开发的技术参考书。本书丰富的实例源代码特别适合初学者根据内容实际运行、体会，举一反三，以掌握SystemC进行应用系统设计。 -SystemC system on chip design source : books introduced : SystemC has been proven in practice is an excellent system design description language, it can be completed from the system level to the door, from hardware to software, from design to verification of all description. SystemC has 2.01 as a stable version submitted to the IEEE, the application of international standards. The book to tie in electronic engineering at Tsinghua University SystemC related courses and preparation of teaching. Book nine chapters, including : hardware description language development history; SystemC is the historical background and system-on-chip design methodology outlined; SystemC basic grammar; SystemC register-transfer-level design and synthesis of SystemC language subset, as well as design experience b
Platform: | Size: 2640735 | Author: c.li | Hits:

[Compress-Decompress algrithms] jpeg_encoder

Description: 完整的jpeg encoder verilog code,DCT部分採用1991 IEEE transection paper,利用skew circular convolution來實現精簡電路-complete jpeg encoder Verilog code, DCT is partly based on the IEEE 1991 transection paper, using skew circular convolutions to achieve streamlining circuit
Platform: | Size: 25437 | Author: 李寧 | Hits:

[Other resource] DCT_1D

Description: 一维DCT变换的verilog源码，可用于JPEG算法优化的参考。程序中用到的算法称为“扭卷积”，可参考相关IEEE paper
Platform: | Size: 54458 | Author: 楚天 | Hits:

[Other] UART_VHDL

Description: 由于微电子学和计算机科学的迅速发展，给EDA(电子设计自动化)行业带来了巨大的变化。特别是进入20世纪90年代后，电子系统已经从电路板级系统集成发展成为包括ASIC、FPGA/CPLD和嵌入系统的多种模式。可以说EDA产业已经成为电子信息类产品的支柱产业。EDA之所以能蓬勃发展的关键因素之一就是采用了硬件描述语言(HDL)描述电路系统。就FPGA和CPLD开发而言，比较流行的HDL主要有Verilog HDL、VHDL、ABEL-HDL和 AHDL 等，其中VHDL和Verilog HDL因适合标准化的发展方向而最终成为IEEE标准。-As the microelectronics and the rapid development of computer science, to the EDA (electronic design automation) industry, has brought great changes. Especially the beginning of the 20th century, 90 years, the electronic system has moved from the circuit board-level systems integration to develop into, including ASIC, FPGA/CPLD and embedded systems a variety of modes. Can be said that EDA industry, electronic information products has become a pillar industry. EDA has been able to flourish, one of the key factors is the use of a hardware description language (HDL) description of the electronic circuitry. On the FPGA and CPLD development, the more popular HDL mainly Verilog HDL, VHDL, ABEL-HDL, and AHDL etc., in which VHDL and Verilog HDL because of the direction for the development of standardization eventually become IEEE standard.
Platform: | Size: 290816 | Author: lilei | Hits:

[VHDL-FPGA-Verilog] PalnitkarVerilogHDL

Description: Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. The informationpresented is fully compliant with the IEEE 1364-2001 Verilog HDL standard.
Platform: | Size: 1723392 | Author: Amir | Hits:

[Embeded-SCM Develop] iverilog-0.9.2

Description: iverilog是verilog仿真综合工具，能够将verilog源代码编译为不同的目标文件-Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format
Platform: | Size: 1477632 | Author: fanyuchuan | Hits:

[VHDL-FPGA-Verilog] rk

Description: this code is Universal Asynchronous Transreciver this project is IEEE 2008 standard this project is done by my personal and i had verilog code.
Platform: | Size: 5943296 | Author: chandu | Hits:

[VHDL-FPGA-Verilog] modelsim_guide_cn

Description: 使用ModelSim进行设计仿真ModelSim为HDL仿真工具，我们可以利用该软件来实现对所设计的VHDL或Verilog程序进行仿真，支持IEEE常见的各种硬件描述语言标准。可以进行两种语言的混合仿真，但推荐大家只对一种语言仿真。ModelSim常见的版本分为ModelSim XE和ModelSim SE两种，ModelSim版本更新很快-Design simulation using ModelSim HDL simulator ModelSim is, we can use the software to achieve the program designed to simulate VHDL or Verilog, to support a variety of common IEEE standard hardware description language. Mixture of two languages ​ ​ can be simulated, but recommend only one language simulation. Common version of ModelSim and ModelSim SE ModelSim XE is divided into two types, ModelSim version update soon
Platform: | Size: 342016 | Author: 谢明 | Hits:

[VHDL-FPGA-Verilog] floating_point_multiplier_verilog

Description: This code has written in verilog and it can multiply two floating point number with IEEE 754 standards and the out put of this code is in IEEE 754 standard.We have to put input in binary and the out put is also in binary.
Platform: | Size: 1024 | Author: sajad | Hits:

[VHDL-FPGA-Verilog] Verilog-2005

Description: IEEE的英文版VERILOG的教程，里面包括了所有使用方法，很好用-IEEE s English version the VERILOG of tutorials will be English friends can see
Platform: | Size: 3141632 | Author: cc | Hits:

[Communication-Mobile] ethmac10_100M

Description: 以太网IP Core 它实现10/100 Mbps的MAC控制器功能。它是在IEEE802.3和802.3u 标准下设计实现的。-The Ethernet IP Core is a 10/100 Media Access Controller (MAC). It consists of a synthesizable Verilog RTL core that provides all features necessary to implement the Layer 2 protocol of the Ethernet standard. It is designed to run according to the IEEE 802.3 and 802.3u specifications that define the 10 Mbps and 100 Mbps Ethernet standards, respectively.
Platform: | Size: 18925568 | Author: haizi | Hits:

[Other] Verilog-digital-system-design

Description: 全书共分4部分。第一部分共8章，即Verilog数字设计基础篇，可作为本科生的入门教材。第二部分共10章，即设计和验证篇，可作为本科高年级学生或研究生学习数字系统设计的参考书。第三部分为实践篇，共提供12个上机练习和实验范例。第四部分是语法篇，即Verilog 硬件描述语言参考手册；IEEE Verilog13642001标准简介，以反映Verilog语法的最新变化，可供读者学习、查询之用。-The book is divided into four parts. The first part of Chapter 8, Verilog Digital Design Basics, can be used as undergraduate introductory textbook. The second part of 10 chapters, the design and verification of papers, reference books can be used as a senior undergraduate students or graduate study digital system design. The third part is the practice papers, providing a total of 12 on exercises and experimental examples. The fourth part is the syntax articles, Verilog hardware description language reference manual Introduction to IEEE Verilog13642001 standards, to reflect the latest changes in the Verilog syntax for readers to learn inquiry.
Platform: | Size: 17120256 | Author: 虫虫 | Hits:

[VHDL-FPGA-Verilog] IEEE-Std-1364.1-2002-Verilog-RTL-Synthesys

Description: IEEE Std 1364.1-2002 Verilog RTL Synthesys
Platform: | Size: 380928 | Author: max | Hits:

[VHDL-FPGA-Verilog] IEEE-Std-1364-2001-Verilog-LRM

Description: IEEE Std 1364-2001 Verilog LRM
Platform: | Size: 2177024 | Author: max | Hits:

[VHDL-FPGA-Verilog] ethernet.tar

Description: verilog写的以太网硬件模型，使用xilinx FPGA，ieee802.3ae-an ethernet model in Verilog，using a Xilinx FPGA，and the function：IEEE 802.3ae Media Access Control (MAC) Parameters, Physical Layers, and Management Parameters for 10 Gb/s Operation
Platform: | Size: 788480 | Author: AricSnow | Hits:

[Other] Low-Error-and-Hardware-Efficient-Fixed-Width-Mult

Description: VERILOG Code for IEEE Paper Low-Error and Hardware-Efficient Fixed-Width Multiplier by Using the Dual-Group Minor Input Correction Vector to Lower Input Correction Vector Compensation Error Run by ModelSim 6.2 software Here paper output and modified paper output can be provided. Phase-1 folder consists of paper output High speed msb multiplication. In phase-2 folder consists of slight change before the multiplication process check the if the multiplication result will give msb or not , if it s possible continue multiplication process otherwise zero can be put on the result.
Platform: | Size: 783360 | Author: anandg | Hits:

[Books] IEEE_Verilog_2001

Description: IEEE VERILOG 2001 标准-IEEE VERILOG 2001 standard
Platform: | Size: 2174976 | Author: 李晨 | Hits:

[Other] Verilog-

Description: Verilog hardware description language-IEEE Std 1364-2001 Standard Verilog hardware description language
Platform: | Size: 2174976 | Author: george | Hits:

[Other] IEEE-Standard-for-Verilog

Description: IEEE Standard for Verilog
Platform: | Size: 3252224 | Author: Yan Tian | Hits:

[Software Engineering] verilog-ieee

Description: The Verilog ¤ Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs the communication of hardware design data and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language. Keywords: computer, computer languages, digital systems, electronic systems, hardware, hardware description languages, hardware design, HDL, PLI, programming language interface, Verilog HDL, Verilog PLI, Verilog ¤-The Verilog ¤ Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs the communication of hardware design data and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language. Keywords: computer, computer languages, digital systems, electronic systems, hardware, hardware description languages, hardware design, HDL, PLI, programming language interface, Verilog HDL, Verilog PLI, Verilog ¤
Platform: | Size: 2177024 | Author: bkaraca | Hits:
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